1. Field of the Invention
The present invention relates to a data processing system in which a plurality of masters share one or more slaves.
2. Description of the Prior Art
When a plurality of masters share one or more slaves via busses, an address conversion mechanism for address conversion from an address space managed by each master into a corresponding address space managed by the shared slave(s) is generally provided to efficiently use the shared slave(s). Herein, a master is a microprocessor, DSP (Digital Signal Processor), DMA (Direct Memory Access) controller, or the like and a slave is a memory, peripheral I/O (input/output) controller, or the like. For example, when a shared slave is a memory, masters are made to use empty regions dispersed on the memory as a continuous region by means of address conversion, so that there is no need to ensure an extra static continuous region. This results in reduction in memory usage.
There are various embodiments of an address conversion mechanism. Of those embodiments, as shown in FIG. 7, a method in which an address conversion table that is an address correspondence table used for address conversion is stored in a shared slave memory and part of information of the address conversion table is fetched to a buffer (conversion table buffer) and used for an address conversion is generally adopted. If there is not necessary information for address conversion of an access on the conversion table buffer, the access is temporarily held in a waiting state in a command input control section, the conversion table buffer is updated by accessing the address conversion table by means of a buffer update control section, and address conversion is performed according to the updated information. If there is information on the buffer, a time for referring to the address conversion table on the memory can be saved and address conversion can be performed.
When a plurality of masters access a shared slave, it is necessary that respective bus accesses from the masters are arbitrated and ordered on one bus and then the bus is connected to the shared slave. As shown in FIG. 8A, a plurality of accesses are arbitrated and then the address conversion mechanism is mounted (see JP61026167A). In FIG. 8B, the address conversion mechanism is mounted on each of the masters and, after address conversion is performed, accesses are arbitrated (see EP1067461A1).
When the address conversion mechanism is mounted in a subsequent stage of arbitration of bus accesses, as shown in FIG. 8A, address conversion for all master accesses can be performed by a single address conversion mechanism. Also, since the address conversion mechanism is mounted at a point close to the shared slave, only a short time for reading table information to the buffer is needed when the address conversion table is stored in the shared slave. On the other hand, if in performing address conversion for an access from one master, there is not necessary information in a buffer and the buffer has to be updated, all subsequent accesses from another master are kept waiting during a latency time for update and, thus a problem arises in that the performance of a master, specifically, a processor or the like, requiring low latency access is largely influenced.
When address conversion is performed in a previous stage of arbitration of bus accesses, as shown in FIG. 8B, the problem in which a buffer update latency time of one master affects accesses of other masters does not arise. However, a time for arbitrating accesses of another master is added to a time for accessing the address conversion table on the shared slave, so a time for updating a buffer becomes very long. Furthermore, many address conversion mechanisms have to be mounted.
As described above, when any one of the known methods for mounting an address conversion mechanism is used, some unacceptable problem arises for each method.